15.4 Floating-Point Control Registers
Bits 22:18 are unimplemented and must be set to zero. All other bits may be read or written using Control Move instructions from or to Coprocessor 1 (subfunctions CFC1 or CTC1). These move instructions are fully interlocked; they are delayed in the decode stage until all previous instructions have been graduated, and no subsequent instruction is decoded until they have been completed.
Figure 15-7 Floating-Point Status Register (FSR)
Condition Bits [31:25,23]: The Condition bits indicate the result of floating-point compare instructions. The active list keeps track of these bits.
Cause Bits [17:12]: Each functional unit can detect exceptional cases in their function codes, operands, or results. These cases are indicated by setting one of six specific Cause bits. The Cause bits indicate the status of the floating-point arithmetic instruction which graduated most recently or caused an exception to be taken. The FSR is not modified by load, store, or move instructions. All cause bits, except E, have corresponding Enable and Flag bits in the FSR.
E Unimplemented operation: the execution unit does not perform the specified operation. This exception is always enabled.
V Invalid operation: this operation is not valid for the given operands.
Z Division by zero: (divide unit only) the result of division by zero is not defined.
O Overflow: the result is too large in magnitude to be correctly represented in the result format.
U Underflow: the result is too small in magnitude to be correctly represented in the result format.
I Inexact Result: the result cannot be represented exactly.
Enable Bits [11:7]: The five Enable bits individually enable (when set to a 1) or disable (when set to a 0) exceptions when the corresponding Cause bit is set.
Flag Bits [6:2]: One of the five Flag bits is set when a floating-point arithmetic instruction graduates, if the corresponding Cause bit is set. The Flag bits are sticky and remain set until the FSR is written. Thus, the Flag bits indicate the status of all floating-point instructions graduated since the FSR was last written. The Flag bits are not modified for any instructions which cause an exception to be taken.
Round Mode [1:0]: RM bits select one of the four IEEE rounding modes. Most floating-point results cannot be precisely represented by the 32-bit or 64-bit register formats, and must be truncated and rounded to a representable value. The modes selected by the RM bit values are:
0: RN, round to nearest representable value. If two values are equally near, set the lowest bit to zero.
1: RZ, round toward zero. Round to the closest value whose magnitude is not greater than the result.
2: RP, round to plus infinity. Round to the closest value whose magnitude is not less than the result.
3: RM, round to minus infinity. Round to the closest value whose magnitude is not greater.
The Round and Enable bits only change when the FSR is written by a CTC1 (Move To Coprocessor 1 Control Register) instruction. Each CTC1 instruction is executed sequentially, after all previous floating-point instructions have been completed, so these FSR bits do not change while any floating-point instruction is active. These bits are broadcast from the graduation unit to all the floating-point functional units.
If any Cause bit and its corresponding Enable bit are both set, an exception is taken after FSR has been modified. The CTC1 instruction is aborted; it does not graduate, even though it has changed the processor state.
